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WMPI
2004
ACM
16 years 2 days ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ICT
2004
Springer
131views Communications» more  ICT 2004»
16 years 1 days ago
Fairness and Protection Behavior of Resilient Packet Ring Nodes Using Network Processors
The Resilient Packet Ring IEEE 802.17 is an evolving standard for the construction of Local and Metropolitan Area Networks. The RPR protocol scales to the demands of future packet ...
Andreas Kirstädter, Axel Hof, Walter Meyer, E...
IPSN
2004
Springer
16 years 1 days ago
Sensing uncertainty reduction using low complexity actuation
The performance of a sensor network may be best judged by the quality of application specific information return. The actual sensing performance of a deployed sensor network depe...
Aman Kansal, Eric Yuen, William J. Kaiser, Gregory...
CODES
2003
IEEE
15 years 12 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang
CODES
2003
IEEE
15 years 12 months ago
Design optimization of mixed time/event-triggered distributed embedded systems
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
Traian Pop, Petru Eles, Zebo Peng