6111 search results - page 953 / 1223 » Time, Hardware, and Uniformity |
155
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GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
147
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CGO
2008
IEEE
16 years 1 months ago
2008
IEEE
We propose a new instruction, branch-on-random, that is like a standard conditional branch, except rather than specifying the condition on which the branch should be taken, it spe...
165
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FCCM
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents a proto-type autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGA...
167
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GLVLSI
2008
IEEE
16 years 1 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
157
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IPPS
2008
IEEE
16 years 1 months ago
2008
IEEE
Abstract—Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1...