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ISCAS
2006
IEEE
147views Hardware» more  ISCAS 2006»
16 years 23 days ago
Triangular systolic array with reduced latency for QR-decomposition of complex matrices
- The novel CORDIC-based architecture of the these weights (combiner unit). The implementation of the Triangular Systolic Array for QRD of large size complex combiner unit is rathe...
Alexander Maltsev, V. Pestretsov, Roman Maslenniko...
ISCAS
2006
IEEE
150views Hardware» more  ISCAS 2006»
16 years 23 days ago
A character size optimization technique for throughput enhancement of character projection lithography
— We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw...
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryo...
ISCAS
2006
IEEE
131views Hardware» more  ISCAS 2006»
16 years 23 days ago
Static generator model for analog power flow computation
—Accurate analog models of power system components are required in order to realize an analog computation engine for power systems. Analog computation is an area of continued int...
Aaron St. Leger, Chika O. Nwankpa
ISCAS
2006
IEEE
114views Hardware» more  ISCAS 2006»
16 years 23 days ago
System for deposition and characterization of polypyrrole/gold bilayer hinges
— We report on a custom designed system for the deposition and characterization of polypyrrole bilayer actuators. Unlike conventional commercial electrochemical cells and potenti...
Edward Choi, Yingkai Liu, Elisabeth Smela, Andreas...
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
16 years 23 days ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman