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EUROPAR
1999
Springer
15 years 11 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
EUROPAR
2009
Springer
15 years 10 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
ACMMSP
2006
ACM
226views Hardware» more  ACMMSP 2006»
15 years 10 months ago
Smarter garbage collection with simplifiers
We introduce a method for providing lightweight daemons, called simplifiers, that attach themselves to program data. If a data item has a simplifier, the simplifier may be run aut...
Melissa E. O'Neill, F. Warren Burton
MOVEP
2000
136views Hardware» more  MOVEP 2000»
15 years 10 months ago
UPPAAL - Now, Next, and Future
Uppaal is a tool for modeling, simulation and verification of real-time systems, developed jointly by BRICS at Aalborg University and the Department of Computer Systems at Uppsala ...
Tobias Amnell, Gerd Behrmann, Johan Bengtsson, Ped...
SIGMETRICS
2008
ACM
161views Hardware» more  SIGMETRICS 2008»
15 years 6 months ago
Bound analysis of closed queueing networks with workload burstiness
Burstiness and temporal dependence in service processes are often found in multi-tier architectures and storage devices and must be captured accurately in capacity planning models...
Giuliano Casale, Ningfang Mi, Evgenia Smirni