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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 11 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
187
Voted
SIGMETRICS
2010
ACM
201views Hardware» more  SIGMETRICS 2010»
15 years 11 months ago
Load balancing via random local search in closed and open systems
In this paper, we analyze the performance of random load resampling and migration strategies in parallel server systems. Clients initially attach to an arbitrary server, but may s...
Ayalvadi Ganesh, Sarah Lilienthal, D. Manjunath, A...
HPCA
2000
IEEE
15 years 11 months ago
A Prefetching Technique for Irregular Accesses to Linked Data Structures
Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there i...
Magnus Karlsson, Fredrik Dahlgren, Per Stenstr&oum...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 11 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
ICCAD
1999
IEEE
66views Hardware» more  ICCAD 1999»
15 years 11 months ago
Timing-safe false path removal for combinational modules
A delay abstraction of a combinational module is a compact representation of the delay information of the module, which carries effective pin-to-pin delay for each primary-input/pr...
Yuji Kukimoto, Robert K. Brayton