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CONIELECOMP
2011
IEEE
14 years 10 months ago
FPGA design and implementation for vertex extraction of polygonal shapes
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
Jorge Martínez-Carballido, Jorge Guevara-Es...
ISCAS
2011
IEEE
342views Hardware» more  ISCAS 2011»
14 years 10 months ago
Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
—Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS...
Ying-Xun Lai, Yueh-Min Huang, Chin-Feng Lai, Ljilj...
ETS
2011
IEEE
220views Hardware» more  ETS 2011»
14 years 6 months ago
Structural In-Field Diagnosis for Random Logic Circuits
—In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional ...
Alejandro Cook, Melanie Elm, Hans-Joachim Wunderli...
ETS
2011
IEEE
224views Hardware» more  ETS 2011»
14 years 6 months ago
AVF Analysis Acceleration via Hierarchical Fault Pruning
—The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way ...
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas...
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
14 years 6 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...