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TVLSI
2010
15 years 1 months ago
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
DATE
2011
IEEE
223views Hardware» more  DATE 2011»
14 years 10 months ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...
173
Voted
HPCA
2011
IEEE
14 years 10 months ago
Shared last-level TLBs for chip multiprocessors
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...
Abhishek Bhattacharjee, Daniel Lustig, Margaret Ma...
ISQED
2011
IEEE
398views Hardware» more  ISQED 2011»
14 years 10 months ago
Switching constraint-driven thermal and reliability analysis of Nanometer designs
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...
Srini Krishnamoorthy, Vishak Venkatraman, Yuri Apa...
VTS
2011
IEEE
278views Hardware» more  VTS 2011»
14 years 10 months ago
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...
Rudrajit Datta, Nur A. Touba