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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer
ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
15 years 8 months ago
Computation Tree Regular Logic for Genetic Regulatory Networks
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
Radu Mateescu, Pedro T. Monteiro, Estelle Dumas, H...
ATVA
2008
Springer
104views Hardware» more  ATVA 2008»
15 years 8 months ago
A Direct Algorithm for Multi-valued Bounded Model Checking
Multi-valued Model Checking is an extension of classical, two-valued model checking with multi-valued logic. Multi-valuedness has been proved useful in expressing additional inform...
Jefferson O. Andrade, Yukiyoshi Kameyama
ATVA
2008
Springer
143views Hardware» more  ATVA 2008»
15 years 8 months ago
Automating Algebraic Specifications of Non-freely Generated Data Types
Abstract. Non-freely generated data types are widely used in case studies carried out in the theorem prover KIV. The most common examples are stores, sets and arrays. We present an...
Andriy Dunets, Gerhard Schellhorn, Wolfgang Reif