We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
Prior to this work, all implementations of stack simulation [MGS70] required more than linear time to process an address trace. In particular these implementations are often slow ...
This paper establishes a novel model for RFID schemes where readers are not continuously connected to the back office, but only periodically. Furthermore, adversaries are not only ...