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PACS
2000
Springer
121views Hardware» more  PACS 2000»
15 years 10 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
PACS
2000
Springer
118views Hardware» more  PACS 2000»
15 years 10 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
ICCAD
1995
IEEE
127views Hardware» more  ICCAD 1995»
15 years 10 months ago
Hybrid decision diagrams
Abstract: Functions that map boolean vectors into the integers are important for the design and veri cation of arithmetic circuits. MTBDDs and BMDs have been proposed for represent...
Edmund M. Clarke, Masahiro Fujita, Xudong Zhao
ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
15 years 10 months ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 10 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...