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FPL
2006
Springer
113views Hardware» more  FPL 2006»
15 years 10 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...
ASPDAC
2001
ACM
105views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Toward better wireload models in the presence of obstacles
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk S...
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
ASPDAC
2001
ACM
103views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Efficient minimum spanning tree construction without Delaunay triangulation
Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs o...
Hai Zhou, Narendra V. Shenoy, William Nicholls
ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
15 years 10 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson