6111 search results - page 865 / 1223 » Time, Hardware, and Uniformity |
170
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RTSS
1989
IEEE
15 years 11 months ago
1989
IEEE
A new fault tolerant architecture that provides tolerance to a broad scope of hardware, software, and communications faults is being developed. This architecture relies on widely ...
171
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AICCSA
2007
IEEE
15 years 10 months ago
2007
IEEE
Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In noncontiguous allocation, a ...
158
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
134
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
168
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...