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156
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ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
15 years 11 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
ISLPED
1999
ACM
91views Hardware» more  ISLPED 1999»
15 years 11 months ago
Stochastic modeling of a power-managed system: construction and optimization
-- The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing ce...
Qinru Qiu, Qing Wu, Massoud Pedram
165
Voted
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
ICCAD
1999
IEEE
113views Hardware» more  ICCAD 1999»
15 years 11 months ago
Attractor-repeller approach for global placement
Traditionally, analytic placement used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together. The...
Hussein Etawil, Shawki Areibi, Anthony Vannelli
190
Voted
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 11 months ago
Power minimization using system-level partitioning of applications with quality of service requirements
Design systems to provide various quality of service (QoS) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless commun...
Gang Qu, Miodrag Potkonjak