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ASPDAC
2000
ACM
117views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Improved algorithms for hypergraph bipartitioning
Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
15 years 11 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
15 years 11 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley
ISPD
2000
ACM
86views Hardware» more  ISPD 2000»
15 years 11 months ago
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
Li-Fu Chang, Keh-Jeng Chang, Robert Mathews
ISPD
2000
ACM
97views Hardware» more  ISPD 2000»
15 years 11 months ago
Routability-driven repeater block planning for interconnect-centric floorplanning
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and der...
Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh