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ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
15 years 11 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
15 years 11 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
MICRO
2000
IEEE
84views Hardware» more  MICRO 2000»
15 years 11 months ago
The impact of delay on the design of branch predictors
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While ex...
Daniel A. Jiménez, Stephen W. Keckler, Calv...
MICRO
2000
IEEE
124views Hardware» more  MICRO 2000»
15 years 11 months ago
Calpa: a tool for automating selective dynamic compilation
Selective dynamic compilation systems, typically driven by annotations that identify run-time constants, can achieve significant program speedups. However, manually inserting ann...
Markus Mock, Craig Chambers, Susan J. Eggers
MSS
2000
IEEE
81views Hardware» more  MSS 2000»
15 years 11 months ago
Compact Holographic Read/Write Memory
— We examine the primary challenges for building a practical and competitive holographic random access memory (HRAM) system, specifically size, speed, and cost. We show that a fa...
Wenhai Liu, Demetri Psaltis