6111 search results - page 845 / 1223 » Time, Hardware, and Uniformity |
171
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ATS
2000
IEEE
15 years 11 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
179
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ATS
2000
IEEE
15 years 11 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
185
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
203
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
In [1], Murata et al introduced an elegant representation of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated a...
162
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ICCAD
2000
IEEE
15 years 11 months ago
2000
IEEE
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...