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DATE
2002
IEEE
98views Hardware» more  DATE 2002»
15 years 12 months ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
DATE
2002
IEEE
128views Hardware» more  DATE 2002»
15 years 12 months ago
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG
In this paper, we deal with arbitrary convex and concave rectilinear module packing using the Transitive Closure Graph (TCG) representation. The geometric meanings of modules are ...
Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
DSD
2002
IEEE
90views Hardware» more  DSD 2002»
15 years 12 months ago
Simplifying Instruction Issue Logic in Superscalar Processors
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
Toshinori Sato, Itsujiro Arita
ICECCS
2002
IEEE
79views Hardware» more  ICECCS 2002»
15 years 12 months ago
A Framework for Performability Modeling of Messaging Services in Distributed Systems
Messaging services are a useful component in distributed systems that require scalable dissemination of messages (events) from suppliers to consumers. These services decouple supp...
Srinivasan Ramani, Katerina Goseva-Popstojanova, K...
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
15 years 11 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin