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162
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
171
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
In this paper we propose a new harmonic balance simulation methodology based on a linear-centric modeling approach. A linear circuit representation of the nonlinear devices and as...
169
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
159
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximati...
175
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...