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DATE
2003
IEEE
103views Hardware» more  DATE 2003»
16 years 7 days ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
16 years 7 days ago
Fast Computation of Data Correlation Using BDDs
Data correlation is a well-known problem that causes difficulty in VLSI testing. Based on a correlation metric, an efficient heuristic to select BIST registers has been proposed...
Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maci...
ICCAD
2003
IEEE
151views Hardware» more  ICCAD 2003»
16 years 7 days ago
On Compacting Test Response Data Containing Unknown Values
The design of a test response compactor called a Block Compactor is given. Block Compactors belong to a new class of compactors called Finite Memory Compactors. Different from spa...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janu...
ICDCS
2003
IEEE
16 years 7 days ago
Decision-Support Workload Characteristics on a Clustered Database Server from the OS Perspective
A range of database services are being offered on clusters of workstations today to meet the demanding needs of applications with voluminous datasets, high computational and I/O r...
Yanyong Zhang, Jianyong Zhang, Anand Sivasubramani...
IEEEPACT
2003
IEEE
16 years 6 days ago
Picking Statistically Valid and Early Simulation Points
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
Erez Perelman, Greg Hamerly, Brad Calder