6111 search results - page 827 / 1223 » Time, Hardware, and Uniformity |
184
click to vote
FCCM
2005
IEEE
16 years 17 days ago
2005
IEEE
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
164
click to vote
FCCM
2005
IEEE
16 years 17 days ago
2005
IEEE
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse o...
175
click to vote
ICCAD
2005
IEEE
16 years 17 days ago
2005
IEEE
— Balanced truncation (BT) model order reduction (MOR) is known for its superior accuracy and computable error bounds. Balanced stochastic truncation (BST) is a particular BT pro...
186
click to vote
ICECCS
2005
IEEE
16 years 17 days ago
2005
IEEE
Component-based technology is increasingly adopted to speed up the development of complex software through component reuse. Unfortunately, the lack of complete information about r...
180
click to vote
IPPS
2005
IEEE
16 years 16 days ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...