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DATE
2007
IEEE
128views Hardware» more  DATE 2007»
16 years 1 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 1 months ago
Performance aware secure code partitioning
Many embedded applications exist where decisions are made using sensitive information. A critical issue in such applications is to ensure that data is accessed only by authorized ...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ri...
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
16 years 1 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
16 years 1 months ago
A novel technique to use scratch-pad memory for stack management
Extensive work has been done for optimal management of scratch-pad memory (SPM) all assuming that the SPM is assigned a fixed address space. The main target objects to be placed o...
Soyoung Park, Hae-woo Park, Soonhoi Ha
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
16 years 1 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...