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DATE
2008
IEEE
66views Hardware» more  DATE 2008»
16 years 1 months ago
Optimal Margin Computation for At-Speed Test
— In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly highe...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
16 years 1 months ago
Developing Mesochronous Synchronizers to Enable 3D NoCs
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
Igor Loi, Federico Angiolini, Luca Benini
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
16 years 1 months ago
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
Tilo Meister, Jens Lienig, Gisbert Thomke
DATE
2008
IEEE
123views Hardware» more  DATE 2008»
16 years 1 months ago
Test Strategies for Low Power Devices
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...
C. P. Ravikumar, M. Hirech, X. Wen
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 1 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek