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ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
16 years 1 months ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
TEI
2010
ACM
144views Hardware» more  TEI 2010»
16 years 1 months ago
Tangible jukebox: back to palpable music
Since commercial musical recordings became available about a century ago and until very recently, they had always been distributed by means of a physical support. Nowadays that re...
Daniel Gallardo, Sergi Jordà
ATS
2009
IEEE
117views Hardware» more  ATS 2009»
16 years 1 months ago
N-distinguishing Tests for Enhanced Defect Diagnosis
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith...
ISQED
2009
IEEE
136views Hardware» more  ISQED 2009»
16 years 1 months ago
NBTI aware workload balancing in multi-core systems
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet ...
ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
16 years 1 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong