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ICCAD
2001
IEEE
127views Hardware» more  ICCAD 2001»
16 years 3 months ago
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
Gang Qu
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
16 years 3 months ago
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
Radu Marculescu, Amit Nandi, Luciano Lavagno, Albe...
ICCAD
2001
IEEE
163views Hardware» more  ICCAD 2001»
16 years 3 months ago
Predicting the Performance of Synchronous Discrete Event Simulation Systems
In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
Jinsheng Xu, Moon-Jung Chung
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
16 years 3 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
231
Voted
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
16 years 1 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...