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ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
16 years 3 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 3 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
16 years 3 months ago
Computational geometry based placement migration
Placement migration is a critical step to address a variety of postplacement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To...
Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhi...
ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
16 years 3 months ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
16 years 3 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm