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ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
16 years 4 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
16 years 4 months ago
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.
We propose VAriable Length Value Encoding (VALVE) technique to reduce the power consumption in the off-chip data buses. While past research has focused on encoding fixed length da...
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, ...
ICCD
2005
IEEE
169views Hardware» more  ICCD 2005»
16 years 4 months ago
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...
Wei Zhang, Niraj K. Jha
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 4 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 4 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes