Sciweavers

6111 search results - page 788 / 1223
» Time, Hardware, and Uniformity
Sort
View
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
16 years 4 months ago
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Saraju P. Mohanty, Elias Kougianos
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
16 years 4 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCD
2005
IEEE
119views Hardware» more  ICCD 2005»
16 years 4 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
16 years 4 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
16 years 4 months ago
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
Prateek Pujara, Aneesh Aggarwal