Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...