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VLSID
2002
IEEE
132views VLSI» more  VLSID 2002»
16 years 7 months ago
VLSI Architecture for a Flexible Motion Estimation with Parameters
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsu...
ICCD
2008
IEEE
370views Hardware» more  ICCD 2008»
16 years 4 months ago
Simulation points for SPEC CPU 2006
— Increasing sizes of benchmarks make detailed simulation an extremely time consuming process. Statistical techniques such as the SimPoint methodology have been proposed in order...
Arun A. Nair, Lizy K. John
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
16 years 4 months ago
A high-performance parallel CAVLC encoder on a fine-grained many-core system
—This paper presents a high-performance parallel context-based adaptive length coding (CAVLC) encoder implemented on a fine-grained many-core system. The software encoder is desi...
Zhibin Xiao, Bevan Baas
ICCD
2008
IEEE
136views Hardware» more  ICCD 2008»
16 years 4 months ago
A resource efficient content inspection system for next generation Smart NICs
— The aggregate power consumption of the Internet is increasing at an alarming rate, due in part to the rapid increase in the number of connected edge devices such as desktop PCs...
Karthik Sabhanatarajan, Ann Gordon-Ross
ICCD
2008
IEEE
498views Hardware» more  ICCD 2008»
16 years 4 months ago
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
Hao Xu, Ranga Vemuri, Wen-Ben Jone