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ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
16 years 1 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
CODES
2007
IEEE
16 years 1 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS ad...
Chichyang Chen, Paul Chow
MICRO
2005
IEEE
133views Hardware» more  MICRO 2005»
16 years 19 days ago
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and addition...
Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
16 years 14 days ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks