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HPCA
1996
IEEE
15 years 11 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
DSN
2007
IEEE
15 years 11 months ago
Performability Models for Multi-Server Systems with High-Variance Repair Durations
We consider cluster systems with multiple nodes where each server is prone to run tasks at a degraded level of service due to some software or hardware fault. The cluster serves t...
Hans-Peter Schwefel, Imad Antonios
DELTA
2004
IEEE
15 years 10 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
HPDC
1995
IEEE
15 years 10 months ago
A High Speed Implementation of Adaptive Shaping for Dynamic Bandwidth Allocation
Most algorithms proposed for controlling traffic prior to entering ATM networks are based on static mechanisms. Such static control mechanisms do not account for the dynamics of ...
Cameron Braun, V. Sirkay, H. Uriona, Srini W. Seet...
CCGRID
2008
IEEE
15 years 9 months ago
Using Probabilistic Characterization to Reduce Runtime Faults in HPC Systems
Abstract--The current trend in high performance computing is to aggregate ever larger numbers of processing and interconnection elements in order to achieve desired levels of compu...
Jim M. Brandt, Bert J. Debusschere, Ann C. Gentile...