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RTSS
2008
IEEE
16 years 1 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
CNSR
2007
IEEE
104views Communications» more  CNSR 2007»
16 years 1 months ago
Performance Analysis of Web Service Replica Selection in an Extranet
Providing web service replicas improves the overall system performance and redundancy for hardware failures. In Business-to-Business, this may be particularly interesting for orga...
Partheeban Chandrasekaran, Shikharesh Majumdar, Ch...
ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
16 years 1 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
GPCE
2007
Springer
16 years 1 months ago
42: programmable models of computation for a component-based approach to heterogeneous embedded systems
Every notion of a component for the development of embedded systems has to take heterogeneity into account: components may be hardware or software or OS, synchronous or asynchrono...
Florence Maraninchi, Tayeb Bouhadiba
238
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IESS
2007
Springer
92views Hardware» more  IESS 2007»
16 years 1 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer