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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
16 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
ICCAD
2005
IEEE
132views Hardware» more  ICCAD 2005»
16 years 20 days ago
Battery optimization vs energy optimization: which to choose and when?
— Batteries are non-ideal energy sources – minimizing the energy consumption of a battery-powered system is not equivalent to maximizing its battery life. We propose an alterna...
Ravishankar Rao, Sarma B. K. Vrudhula
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 11 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
15 years 11 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe