Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...
Jason Cong, Ashok Jagannathan, Glenn Reinman, Mich...
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
The Least Attained Service (LAS) scheduling policy, when used for scheduling packets over the bottleneck link of an Internet path, can greatly reduce the average flow time for sh...
Idris A. Rai, Guillaume Urvoy-Keller, Mary K. Vern...
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky