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DAC
2003
ACM
16 years 8 months ago
Microarchitecture evaluation with physical planning
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...
Jason Cong, Ashok Jagannathan, Glenn Reinman, Mich...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
16 years 1 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
SIGMETRICS
2004
ACM
127views Hardware» more  SIGMETRICS 2004»
16 years 15 days ago
Performance analysis of LAS-based scheduling disciplines in a packet switched network
The Least Attained Service (LAS) scheduling policy, when used for scheduling packets over the bottleneck link of an Internet path, can greatly reduce the average flow time for sh...
Idris A. Rai, Guillaume Urvoy-Keller, Mary K. Vern...
ICCD
2007
IEEE
183views Hardware» more  ICCD 2007»
16 years 4 months ago
Constraint satisfaction in incremental placement with application to performance optimization under power constraints
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
Huan Ren, Shantanu Dutt
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
16 years 4 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky