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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
16 years 4 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
16 years 1 months ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
16 years 1 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
PDIS
1994
IEEE
15 years 11 months ago
Achieving Transaction Scaleup on Unix
Constructing scalable high-performance applications on commodity hardware running the Unix operating system is a problem that must be addressed in several application domains. We ...
Marie-Anne Neimat, Donovan A. Schneider
SIGMETRICS
2008
ACM
101views Hardware» more  SIGMETRICS 2008»
15 years 7 months ago
How to parameterize models with bursty workloads
Although recent advances in theory indicate that burstiness in the service time process can be handled effectively by queueing models (e.g., MAP queueing networks [2]), there is a...
Giuliano Casale, Ningfang Mi, Ludmila Cherkasova, ...