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ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
16 years 18 days ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
16 years 18 days ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
EMSOFT
2004
Springer
16 years 16 days ago
An approach for integrating basic retiming and software pipelining
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
Noureddine Chabini, Wayne Wolf
SAMOS
2004
Springer
16 years 15 days ago
with Wide Functional Units
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
Miquel Pericàs, Eduard Ayguadé, Javi...
ISCAS
2003
IEEE
124views Hardware» more  ISCAS 2003»
16 years 13 days ago
Convergent transfer subgraph characterization and computation
In this paper, we present a precise characterization of the existence of a convergent transfer subgraph in an edge colored directed acyclic graph. Based on the characterization, l...
Wing Ning Li