6111 search results - page 743 / 1223 » Time, Hardware, and Uniformity |
209
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
168
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
184
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VTS
2008
IEEE
16 years 1 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
151
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MSS
2007
IEEE
16 years 1 months ago
2007
IEEE
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
174
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CODES
2006
IEEE
16 years 1 months ago
2006
IEEE
Accurate modeling of communication is a necessary part of system level design for real-time safety-critical applications. For efficient prediction of a system’s performance, Tra...