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EGH
2004
Springer
16 years 17 days ago
Mio: fast multipass partitioning via priority-based instruction scheduling
Real-time graphics hardware continues to offer improved resources for programmable vertex and fragment shaders. However, shader programmers continue to write shaders that require ...
Andrew Riffel, Aaron E. Lefohn, Kiril Vidimce, Mar...
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
16 years 8 days ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
15 years 10 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
SIGMETRICS
2012
ACM
347views Hardware» more  SIGMETRICS 2012»
13 years 9 months ago
Temperature management in data centers: why some (might) like it hot
The energy consumed by data centers is starting to make up a significant fraction of the world’s energy consumption and carbon emissions. A large fraction of the consumed energ...
Nosayba El-Sayed, Ioan A. Stefanovici, George Amvr...