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ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
15 years 11 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
ICCAD
1996
IEEE
127views Hardware» more  ICCAD 1996»
15 years 11 months ago
Comparing models of computation
We give a denotational framework (a "meta model") within which certain properties of models of computation can be understood and compared. It describes concurrent proces...
Edward A. Lee, Alberto L. Sangiovanni-Vincentelli
ICECCS
1996
IEEE
109views Hardware» more  ICECCS 1996»
15 years 11 months ago
Dynamically Reconfigurable Embedded Software - Does It Make Sense?
A dynamically reconfigurable real-time software (DRRTS) paradigm can be used effectively in the design of embedded systems to provide many major advantages over conventional softw...
David B. Stewart, Gaurav Arora
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
15 years 11 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey
IPPS
1994
IEEE
15 years 11 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...