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FPL
2007
Springer
128views Hardware» more  FPL 2007»
16 years 1 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton
ISI
2007
Springer
16 years 1 months ago
Using Digital Chains of Custody on Constrained Devices to Verify Evidence
—A digital chain of custody is an account documenting digital data at a particular place and time. This paper gives a method of validating and authenticating a digital chain of c...
Phillip G. Bradford, Daniel A. Ray
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
16 years 1 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
16 years 1 months ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
16 years 1 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra