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217
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DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
Abstract—To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on t...
160
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DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
217
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DATE
2009
IEEE
2009
IEEE
Analyzing the impact of process variations on parametric measurements: Novel models and applications
16 years 2 months ago
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
181
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DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
178
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DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...