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ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
16 years 4 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
16 years 4 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
16 years 4 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ICCAD
2002
IEEE
149views Hardware» more  ICCAD 2002»
16 years 4 months ago
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
Hiran Tennakoon, Carl Sechen
ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
16 years 4 months ago
Stars in VCC: Complementing Simulation with Worst-Case Analysis
tems. STARS manipulates abstract representations of system components to obtain upper bounds on the number of various events in the system, as well as a bound on the response time....
Felice Balarin