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ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
16 years 4 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
16 years 4 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
16 years 4 months ago
Combining cluster sampling with single pass methods for efficient sampling regimen design
Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further ex...
Paul D. Bryan, Thomas M. Conte
ICCD
2007
IEEE
125views Hardware» more  ICCD 2007»
16 years 4 months ago
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
ICCD
2006
IEEE
92views Hardware» more  ICCD 2006»
16 years 4 months ago
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...
Dan Nicolaescu, Babak Salamat, Alexander V. Veiden...