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DSD
2008
IEEE
104views Hardware» more  DSD 2008»
15 years 7 months ago
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
Efficient utilization of multi-core architectures relies on the partitioning of applications into tasks and mapping the tasks to cores. In some applications (e.g. H.264 video deco...
Magnus Själander, Andrei Terechko, Marc Duran...
CAL
2006
15 years 7 months ago
Probabilistic counter updates for predictor hysteresis and bias
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
Nicholas Riley, Craig B. Zilles
CII
2006
141views more  CII 2006»
15 years 7 months ago
FPGA-based tool path computation: An application for shoe last machining on CNC lathes
Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for s...
Antonio Jimeno, José Luis Sánchez, H...
ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
15 years 7 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
SIGPLAN
2008
15 years 7 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...