Sciweavers

6111 search results - page 681 / 1223
» Time, Hardware, and Uniformity
Sort
View
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 11 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
15 years 11 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello
MICRO
1997
IEEE
127views Hardware» more  MICRO 1997»
15 years 11 months ago
Exploiting Dead Value Information
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...
Milo M. K. Martin, Amir Roth, Charles N. Fischer
251
Voted
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
15 years 11 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 11 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain