Sciweavers

6111 search results - page 680 / 1223
» Time, Hardware, and Uniformity
Sort
View
IEEEPACT
2000
IEEE
15 years 11 months ago
Address Partitioning in DSM Clusters with Parallel Coherence Controllers
Recent research suggests that DSM clusters can benefit from parallel coherence controllers. Parallel controllers require address partitioning and synchronization to avoid handlin...
Ilanthiraiyan Pragaspathy, Babak Falsafi
180
Voted
IPPS
2000
IEEE
15 years 11 months ago
Predicting Performance on SMPs. A Case Study: The SGI Power Challenge
We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andre...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 11 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
DATE
1999
IEEE
74views Hardware» more  DATE 1999»
15 years 11 months ago
FSMD Functional Partitioning for Low Power
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
Enoch Hwang, Frank Vahid, Yu-Chin Hsu
184
Voted
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
15 years 11 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra