6111 search results - page 668 / 1223 » Time, Hardware, and Uniformity |
168
click to vote
DAC
2000
ACM
16 years 8 months ago
2000
ACM
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
202
click to vote
DSN
2007
IEEE
16 years 1 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
180
click to vote
CAV
2007
Springer
16 years 1 months ago
2007
Springer
Liveness temporal properties state that something “good” eventually happens, e.g., every request is eventually granted. In Linear Temporal Logic (LTL), there is no a priori bo...
191
click to vote
GLVLSI
2006
IEEE
16 years 1 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
192
click to vote
ASPDAC
2006
ACM
16 years 1 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...