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FPL
2008
Springer
104views Hardware» more  FPL 2008»
15 years 8 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
164
Voted
VMV
2004
80views Visualization» more  VMV 2004»
15 years 8 months ago
Reducing State Changes with a Pipeline Buffer
A limiting factor in the performance of a rendering system is the number of state changes, i.e., changes of the attributes material, texture, shader program, etc., in the stream o...
Jens Krokowski, Harald Räcke, Christian Sohle...
205
Voted
ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
15 years 8 months ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...
203
Voted
ATVA
2010
Springer
163views Hardware» more  ATVA 2010»
15 years 7 months ago
Automatic Generation of History-Based Access Control from Information Flow Specification
This paper proposes a method for automatically inserting check statements for access control into a given recursive program according to a given security specification. A history-b...
Yoshiaki Takata, Hiroyuki Seki
171
Voted
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 7 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...