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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
15 years 10 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ASPDAC
2009
ACM
113views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Post-routing redundant via insertion with wire spreading capability
—Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transforme...
Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 9 months ago
Defect aware X-filling for low-power scan testing
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
S. Balatsouka, V. Tenentes, Xrysovalantis Kavousia...
219
Voted
ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
15 years 9 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera
ASPDAC
2008
ACM
119views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP proces
- The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugg...
Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chun...