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DATE
2004
IEEE
174views Hardware» more  DATE 2004»
15 years 11 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
15 years 11 months ago
Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance
Dynamic fault-tolerance management (DFTM) was previously introduced as a means of providing environmentand workload-driven adaptation for failure-prone battery powered systems. Th...
Phillip Stanley-Marbell, Diana Marculescu
DATE
2004
IEEE
157views Hardware» more  DATE 2004»
15 years 11 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
DELTA
2004
IEEE
15 years 11 months ago
Towards Analog and Mixed-Signal SOC Design with SystemC-AMS
Systems-on-Chip (SoCs) are heterogeneous by nature as they may integrate digital, analog, RF hardware as well as software components or non electrical parts such as sensors or act...
Alain Vachoux, Christoph Grimm, Karsten Einwich
DSD
2004
IEEE
111views Hardware» more  DSD 2004»
15 years 11 months ago
Memory Requirement Optimization with Loop Fusion and Loop Shifting
Loop fusion and loop shifting are well recognized loop transformations for memory requirement reduction. Stateof-the-art optimizations with loop fusion and shifting are based on h...
Qubo Hu, Martin Palkovic, Per Gunnar Kjeldsberg