Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Dynamic fault-tolerance management (DFTM) was previously introduced as a means of providing environmentand workload-driven adaptation for failure-prone battery powered systems. Th...
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Systems-on-Chip (SoCs) are heterogeneous by nature as they may integrate digital, analog, RF hardware as well as software components or non electrical parts such as sensors or act...
Loop fusion and loop shifting are well recognized loop transformations for memory requirement reduction. Stateof-the-art optimizations with loop fusion and shifting are based on h...