6111 search results - page 640 / 1223 » Time, Hardware, and Uniformity |
273
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ISLPED
1996
ACM
15 years 11 months ago
1996
ACM
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
178
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
The reuse of well-tested and optimized design objects is an important aspect for decreasing design times, increasing design quality, and improving the predictability of designs. R...
221
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
181
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
194
Voted
ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...